This invention relates to a circuit for amplifying an input signal and obtaining true and complementary output signals, and more particularly to a circuit of such kind using insulated-gate type field-effect transistors.
Recently, there has arisen a demand to have a circuit which is adapted to receive a minute TTL (transistor-transistor-logic) input signal and generates true and complementary logic outputs of an amplitude larger than the TTL input signal. Such a circuit finds a wide application, particularly as an address-inverter-buffer in a MOS memory integrated circuit, an input data generating circuit and a chip-selecting logic circuit. In these exemplified applications, the circuit receives, as an external input signal, an address signal, an input data signal or a chip-selecting signal and generates true and complementary output signals which are employed for decoder selection, determination of a level to be written into a memory cell, or prohibition of a data output circuit (for bringing an output data terminal to a high impedance). The requirements for this circuit are enumerated as below:
(1) The circuit should be operated at a low electric power. Since an integrated circuit such as a MOS memory integrated circuit incorporating the mentioned circuit includes a plurality of circuit blocks, there is required a low electric power circuit effecting a dynamic operation.
(2) An external input terminal capacitance should be minimized. This serves as a measure of allowance in an external driving capability in the practical application of a MOS memory integrated circuit or other integrated circuits incorporating the mentioned circuit.
(3) The circuit should provide an accelerated latch function. For enlarging the range of functions of the integrated circuits, it is essential that time to provide an effective input signal level be minimized.
(4) The circuit should provide both true and complementary outputs which are stable logically and well balanced. Requirement for an output high level is such that the rising of the both true and complementary outputs timely coincide with each other and the levels thereof be even. Requirement for an output low level is such that the level thereof should be sufficiently lower than a threshold voltage and should not affect the next stage. A requirement for accelerating an output results in unstable establishment of a logic level of an output, so that these requirements should be fulfilled to the very limits of an allowance. Accordingly, it has been a demand to have a circuit of an arrangement which is simple in action and judgement in achieving desired logical establishment and balance of both the true and complementary outputs.
Prior art circuits are disclosed in U.S. Pat. Nos. 3,938,109 and 3,987,315, which meet more or less the requirements (1) to (4). The circuit shown in FIG. 3 of U.S. Pat. No. 3,938,109 employs an external reference voltage source, while that of U.S. Pat. No. 3,987,315 receives true and complementary version of input signal. These prior art circuits fail to sufficiently satisfy the requirements (2) and (3). Improvement has been required for obtaining a high speed latch function and a very small input capacitance.
It is therefore an object of the present invention to provide a circuit which fulfills the aforesaid requirements to a possible maximum extent.